PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 358

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
SSPOV ............................................................................. 156
SSPSTAT ......................................................................... 136
SSPSTAT Register
Stuff Error ......................................................................... 223
SUBLW ............................................................................ 297
SUBWF .................................................................... 297, 298
SUBWFB .......................................................................... 299
SWAPF ............................................................................ 300
Synchronization ................................................................ 220
Synchronization Rules ..................................................... 220
Synchronization Segment ................................................ 219
Synchronous Serial Port. See SSP
T
TABLRD ........................................................................... 301
TABLWT ........................................................................... 302
Time Quanta .................................................................... 219
Timer Modules
Timer0 .............................................................................. 113
Timer1 .............................................................................. 117
Timer2
Timer3 .............................................................................. 123
Timing Diagrams
DS30475A-page 358
R/W Bit ............................................................. 148, 149
Timer3
Clock Source Edge Select (T0SE Bit) ...................... 115
Clock Source Select (T0CS Bit) ............................... 115
Overflow Interrupt .................................................... 116
Prescaler. See Prescaler, Timer0
Timing Diagram ........................................................ 326
Block Diagram .......................................................... 118
Oscillator .......................................................... 117, 119
Overflow Interrupt ............................................ 117, 119
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ............................ 119, 130
Timing Diagram ........................................................ 326
TMR1H Register ...................................................... 117
TMR1L Register ....................................................... 117
TMR3L Register ....................................................... 123
Block Diagram .......................................................... 122
Postscaler. See Postscaler, Timer2
PR2 Register .................................................... 121, 132
Prescaler. See Prescaler, Timer2
SSP Clock Shift ................................................ 121, 122
TMR2 Register ......................................................... 121
TMR2 to PR2 Match Interrupt .................. 121, 122, 132
Oscillator .......................................................... 123, 125
Overflow Interrupt ............................................ 123, 125
Special Event Trigger (CCP) .................................... 125
TMR3H Register ...................................................... 123
Acknowledge Sequence Timing ............................... 159
Baud Rate Generator with Clock Arbitration ............ 153
BRG Reset Due to SDA Collision ............................ 164
Bus Collision
Bus Collision During a RESTART Condition
(Case 1) ................................................................... 165
Bus Collision During a RESTART Condition
(Case2) .................................................................... 165
Bus Collision During a START Condition (SCL = 0) 164
Bus Collision During a STOP Condition ................... 166
Bus Collision for Transmit and Acknowledge ........... 162
I
I
I
I
2
2
2
2
C Bus Data ............................................................ 336
C Master Mode First Start bit timing ...................... 154
C Master Mode Reception timing .......................... 158
C Master Mode Transmission timing ..................... 157
Block Diagram .................................................. 124
START Condition Timing ................................. 163
Advanced Information
Timing Diagrams and Specifications ............................... 322
Transmit Interrupt ............................................................ 225
Transmit Message Aborting ............................................. 211
Transmit Message Buffering ............................................ 211
Transmit Message Buffers ............................................... 211
Transmit Message flowchart ............................................ 212
Transmit Message Priority ............................................... 211
Transmitter Error Passive ................................................ 226
Transmitter Warning ........................................................ 226
TRISE Register .................................................................. 97
TSTFSZ ........................................................................... 303
TXSTA Register
U
Universal Synchronous Asynchronous Receiver
Transmitter. See USART
USART ............................................................................. 167
Master Mode Transmit Clock Arbitration ................. 161
Repeat Start Condition ............................................ 155
Slave Synchronization ............................................. 144
Slow Rise Time .......................................................... 33
SPI Mode Timing (Master Mode) SPI Mode
SPI Mode Timing (Slave Mode with CKE = 0) ......... 145
SPI Mode Timing (Slave Mode with CKE = 1) ......... 145
Stop Condition Receive or Transmit ........................ 160
Time-out Sequence on Power-up .............................. 32
USART Asynchronous Master Transmission .......... 174
USART Asynchronous Reception ............................ 176
USART Synchronous Reception ............................. 179
USART Synchronous Transmission ........................ 178
Wake-up from SLEEP via Interrupt .......................... 258
A/D Conversion ........................................................ 340
Brown-out Reset (BOR) ........................................... 325
Capture/Compare/PWM (CCP) ............................... 327
CLKOUT and I/O ..................................................... 324
External Clock .......................................................... 322
I
I
Oscillator Start-up Timer (OST) ............................... 325
Parallel Slave Port (PSP) ......................................... 328
Power-up Timer (PWRT) ......................................... 325
Reset ....................................................................... 325
Timer0 and Timer1 .................................................. 326
USART Synchronous Receive ( Master/Slave) ....... 338
USART Synchronous Transmission ( Master/Slave) 337
Watchdog Timer (WDT) ........................................... 325
BRGH Bit ................................................................. 169
Asynchronous Mode ................................................ 173
Baud Rate Generator (BRG) ................................... 169
Serial Port Enable (SPEN Bit) ................................. 167
Synchronous Master Mode ...................................... 177
Synchronous Slave Mode ........................................ 180
2
2
C Bus Data ............................................................ 334
C Bus START/STOP Bits ...................................... 333
Master Mode Timing Diagram ......................... 143
Master Transmission ....................................... 174
Receive Block Diagram ................................... 175
Reception ........................................................ 176
Transmit Block Diagram .................................. 173
Baud Rate Error, Calculating ........................... 169
Baud Rate Formula ......................................... 169
High Baud Rate Select (BRGH Bit) ................. 169
Sampling .......................................................... 169
Reception ........................................................ 179
Timing Diagram, Synchronous Receive .......... 338
Timing Diagram, Synchronous Transmission .. 337
Transmission ................................................... 178
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