PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 218

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
17.7
All nodes on a given CAN bus must have the same
nominal
Non-Return-to-Zero (NRZ) coding, which does not
encode a clock within the data stream. Therefore, the
receive clock must be recovered by the receiving
nodes and synchronized to the transmitters clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges, to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times, to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18CXX8 is implemented using
a DPLL that is configured to synchronize to the incom-
ing data, and provide the nominal timing for the trans-
mitted data. The DPLL breaks each bit time into
multiple segments, made up of minimal periods of time
called the time quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation, and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
FIGURE 17-6: BIT TIME PARTITIONING
DS30475A-page 218
Input Signal
T
Baud Rate Setting
Q
bit
rate.
Sync
The
Q
).
CAN
Segment
Prop
protocol
Advanced Information
uses
Segment 1
Phase
Sample Point
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the baud
rate prescaler and number of time quanta in each seg-
ment.
The nominal bit rate is the number of bits transmitted
per second assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1Mb/s.
Nominal Bit Time is defined as:
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 17-6.
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 [Phase_Seg2)
Nominal Bit Time = T
Phase_Seg1 + Phase_Seg2)
The time segments and also, the nominal bit time, are
made up of integer units of time called time quanta or
T
is programmable from a minimum of 8 T
mum of 25 T
bit time is 1 s, corresponding to a maximum 1 Mb/s
rate.
Q
(see Figure 17-6). By definition, the nominal bit time
T
BIT
= 1 / NOMlNAL BlT RATE
Q
. Also by definition, the minimum nominal
Q
Segment 2
* (Sync_Seg + Prop_Seg +
2000 Microchip Technology Inc.
Phase
Q
to a maxi-