PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 80

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
7.1.2
The Peripheral Interrupt Request (PIR) registers con-
tain the individual flag bits for the peripheral interrupts
(Register 7-5). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
REGISTER 7-4:
DS30475A-page 80
Note 1: Interrupt flag bits are set when an interrupt
2: User software should ensure the appropri-
PIR REGISTERS
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON register).
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCON REGISTER
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable
For details of bit operation see Register 4-3
Unimplemented: Read as '0'
RI: RESET Instruction Flag bit
For details of bit operation see Register 4-3
TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-3
PD: Power-down Detection Flag bit
For details of bit operation see Register 4-3
POR: Power-on Reset Status bit
For details of bit operation see Register 4-3
BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-3
Legend:
R = Readable bit
- n = Value at POR
bit 7
R/W-0
IPEN
R/W-0
LWRT
Advanced Information
U-0
W = Writable bit
’1’ = Bit is set
—
R/W-1
7.1.3
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 7-5). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt
Enable registers (PIE1, PIE2, PIE3). When IPEN is
clear, the PEIE bit must be set to enable any of these
peripheral interrupts.
7.1.4
The Interrupt Priority (IPR) registers contain the individ-
ual
(Register 7-7). Due to the number of peripheral inter-
rupt sources, there are three Peripheral Interrupt Prior-
ity registers (IPR1, IPR2, IPR3). The operation of the
priority bits requires that the Interrupt Priority Enable bit
(IPEN) be set.
7.1.5
The Reset Control (RCON) register contains the bit that
is used to enable prioritized interrupts (IPEN).
RI
priority
PIE REGISTERS
IPR REGISTERS
RCON REGISTER
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-1
TO
bits
for
R/W-1
 2000 Microchip Technology Inc.
PD
the
x = Bit is unknown
peripheral
R/W-0
POR
interrupts
R/W-0
BOR
bit 0