PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 141

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

15.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Additionally, a fourth pin may be used when in any
Slave mode of operation:
• Slave Select (SS) - RA5/SS/AN4
15.3.1
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON1<5:0> and SSPSTAT<7:6>.
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock polarity (Idle state of SCK)
• Data input sample phase (middle or end of data
• Clock edge (output data on rising/falling edge of
• Clock rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 15-1 shows the block diagram of the MSSP
module, when in SPI mode.
 2000 Microchip Technology Inc.
output time)
SCK)
SPI Mode
OPERATION
Advanced Information
FIGURE 15-1: MSSP BLOCK DIAGRAM
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF (SSPSTAT
register), and the interrupt flag bit, SSPIF (PIR regis-
ters), are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1 register), will be set. User software must
clear the WCOL bit so that it can be determined if the
following write(s) to the SSPBUF register completed
successfully.
SDO
SCK
SDI
SS
Note:
I/O pins have diode protection to V
V
SS
.
Read
SS Control
Select
SMP:CKE
Edge
(SPI MODE)
Enable
bit0
Select
Edge
SSPBUF reg
TRIS bit
Data to TX/RX in SSPSR
2
SSPM3:SSPM0
SSPSR reg
PIC18CXX8
Clock Select
4
2
DS30475A-page 141
Write
Prescaler
4, 16, 64
Clock
(
Shift
TMR2 Output
Data Bus
Internal
DD
2
T
and
OSC
)