PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 116

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
10.3
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in soft-
ware by the Timer0 module interrupt service routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut off during SLEEP.
TABLE 10-1:
DS30475A-page 116
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator
Name
Timer0 Interrupt
modes, they are disabled and read as ‘0’.
Timer0 Module’s Low Byte Register
Timer0 Module’s High Byte Register
GIE/GIEH
TMR0ON
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER0
PORTA Data Direction Register
PEIE/GIEL TMR0IE INT0IE
T08BIT
Bit 6
T0CS
Bit 5
Advanced Information
T0SE
Bit 4
(1)
RBIE
Bit 3
PSA
10.4
Timer0 can be set in 16-bit mode by clearing T0CON
T08BIT. Registers TMR0H and TMR0L are used to
access 16-bit timer value.
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 10-1). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of buffered value of TMR0H,
when a write occurs to TMR0L. This allows all 16 bits
of Timer0 to be updated at once.
TMR0IF INT0IF
T0PS2
Bit 2
16-Bit Mode Timer Reads and Writes
T0PS1
Bit 1
T0PS0
Bit 0
RBIF
 2000 Microchip Technology Inc.
POR, BOR
xxxx xxxx
0000 0000
0000 000x
1111 1111
--11 1111
Value on
uuuu uuuu
0000 0000
0000 000u
1111 1111
--11 1111
Value on
RESETS
all other