PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 53

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

 2000 Microchip Technology Inc.
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
Legend:
Note 1:
Filename
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
These registers are reserved on PIC18C658.
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value
of FSR2 offset by WREG
Indirect Data Memory Address Pointer 2 Low Byte
Timer0 register high byte
Timer0 register low byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
TMR0ON
WCOL
GCEN
ADFM
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
—
—
—
TOUTPS3
ACKSTAT
SSPOV
T08BIT
LWRT
Bit 6
CKE
—
—
—
—
—
—
—
—
—
2
C Slave mode. SSP Baud Rate Reload Register in I
TOUTPS2
T1CKPS1
SSPEN
ACKDT
VCFG1
IRVST
T0CS
CHS3
Bit 5
D/A
—
—
—
—
—
—
Advanced Information
TOUTPS1
T1CKPS0
ACKEN
LVDEN
VCFG0
CHS2
T0SE
Bit 4
CKP
—
—
—
—
RI
N
P
Indirect Data Memory Address Pointer 2 High
T1OSCEN
TOUTPS0
SSPM3
PCFG3
T0PS3
LVDL3
RCEN
CHS1
Bit 3
OV
—
—
TO
—
S
TMR2ON
T1SYNC
SSPM2
PCFG2
ADCS2
T0PS2
LVDL2
CHS0
Bit 2
PEN
R/W
PD
—
—
Z
2
C Master mode.
GO/DONE
T2CKPS1
TMR1CS
SSPM1
PCFG1
ADCS1
T0PS1
LVDL1
RSEN
Bit 1
POR
DC
UA
—
—
PIC18CXX8
SWDTEN
T2CKPS0
TMR1ON
SSPM0
PCFG0
ADCS0
T0PS0
LVDL0
ADON
Bit 0
SCS
BOR
SEN
BF
C
DS30475A-page 53
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
00-1 11qq
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
-000 0000
0--- -000
Value on
POR,
BOR
n/a
n/a
n/a
n/a
n/a
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
00-q qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
-000 0000
0--- -000
RESETS
Value on
all other
n/a
n/a
n/a
n/a
n/a
(3)