PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 354

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
D
Data Memory ...................................................................... 48
DAW ................................................................................. 280
DC Characteristics ........................... 313, 314, 315, 316, 317
DECF ............................................................................... 280
DECFSNZ ........................................................................ 281
DECFSZ ........................................................................... 281
Device Differences ........................................................... 349
Device Functionality ......................................................... 184
Direct Addressing ............................................................... 62
E
Electrical Characteristics .................................................. 311
Errata ................................................................................... 7
Error Detection ................................................................. 223
Error Interrupt ................................................................... 226
Error Modes ..................................................................... 224
Error Modes and Error Counters ...................................... 223
Error States ...................................................................... 223
F
Filter/Mask Truth Table .................................................... 216
Firmware Instructions ....................................................... 261
Form Error ........................................................................ 223
G
General Call Address Sequence ...................................... 150
General Call Address Support ......................................... 150
GOTO ............................................................................... 282
H
Hard Synchronization ....................................................... 220
I
I/O Ports ............................................................................. 89
I
I
I
I
DS30475A-page 354
2
2
2
2
C (SSP Module) ............................................................. 147
C Master Mode Reception ............................................. 156
C Master Mode Restart Condition ................................. 155
C Module
General Purpose Registers ........................................ 48
Special Function Registers ........................................ 48
ACK Pulse ................................................ 147, 148, 149
Addressing ............................................................... 148
Block Diagram .......................................................... 147
Read/Write Bit Information (R/W Bit) ............... 148, 149
Reception ................................................................. 149
Serial Clock (RC3/SCK/SCL) ................................... 149
Slave Mode .............................................................. 147
Timing Diagram, Data .............................................. 334
Timing Diagram, Start/Stop Bits ............................... 333
Transmission ............................................................ 149
Acknowledge Sequence timing ................................ 159
Baud Rate Generator ............................................... 153
BRG Block Diagram ................................................. 153
BRG Reset due to SDA Collision ............................. 164
BRG Timing ............................................................. 153
Bus Collision
Acknowledge .................................................... 162
Restart Condition ............................................. 165
Restart Condition Timing (Case1) .................... 165
Restart Condition Timing (Case2) .................... 165
START Condition ............................................. 163
Start Condition Timing ............................. 163, 164
STOP Condition ............................................... 166
STOP Condition Timing (Case1) ..................... 166
STOP Condition Timing (Case2) ..................... 166
Transmit Timing ............................................... 162
Advanced Information
ID Locations ............................................................. 251, 259
INCF ................................................................................ 282
INCFSNZ ......................................................................... 283
INCFSZ ............................................................................ 283
In-Circuit Serial Programming (ICSP) ...................... 251, 259
Indirect Addressing ............................................................ 62
Information Processing Time ........................................... 219
Initiating Message Transmission ..................................... 211
Instruction Cycle ................................................................ 45
Instruction Flow/Pipelining ................................................. 46
Instruction Format ............................................................ 263
Instruction Set .................................................................. 261
Bus Collision timing ................................................. 162
Clock Arbitration ...................................................... 161
Clock Arbitration Timing (Master Transmit) ............. 161
General Call Address Support ................................. 150
Master Mode 7-bit Reception timing ........................ 158
Master Mode Operation ........................................... 152
Master Mode Start Condition ................................... 154
Master Mode Transmission ..................................... 156
Master Mode Transmit Sequence ............................ 152
Multi-Master Mode ................................................... 162
Repeat START Condition timing .............................. 155
STOP Condition Receive or Transmit timing ........... 160
STOP Condition timing ............................................ 159
Waveforms for 7-bit Reception ................................ 149
Waveforms for 7-bit Transmission ........................... 149
FSR Register ............................................................. 61
ADDLW .................................................................... 267
ADDWF .................................................................... 267
ADDWFC ................................................................. 268
ANDLW .................................................................... 268
ANDWF .................................................................... 269
BCF ......................................................................... 270
BSF .................. 269, 270, 271, 272, 273, 275, 276, 291
BTFSC ..................................................................... 274
BTFSS ..................................................................... 274
BTG ......................................................................... 275
CALL ........................................................................ 276
CLRF ............................................................... 277, 295
CLRWDT ................................................................. 277
COMF ...................................................................... 278
CPFSEQ .................................................................. 278
CPFSGT .................................................................. 279
CPFSLT ................................................................... 279
DAW ........................................................................ 280
DECF ....................................................................... 280
DECFSNZ ................................................................ 281
DECFSZ .................................................................. 281
GOTO ...................................................................... 282
INCF ........................................................................ 282
INCFSNZ ................................................................. 283
INCFSZ .................................................................... 283
IORLW ..................................................................... 284
IORWF ..................................................................... 284
MOVFP .................................................................... 286
MOVLB .................................................................... 285
MOVLR ............................................................ 285, 286
MOVLW ................................................................... 287
MOVWF ................................................................... 287
MULLW .................................................................... 288
MULWF .................................................................... 288
NEGW ..................................................................... 289
NOP ......................................................................... 289
RETFIE ............................................................ 291, 292
RETLW .................................................................... 292
2000 Microchip Technology Inc.