PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 146

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
15.3.6
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to trans-
mit/receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from SLEEP.
15.3.7
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-2:
DS30475A-page 146
INTCON
PIR1
PIE1
IPR1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator
Name
SLEEP OPERATION
EFFECTS OF A RESET
Shaded cells are not used by the MSSP in SPI mode.
modes, they are disabled and read ‘0’.
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
PSPIF
PSPIE
PSPIP
WCOL
GIEH
Bit 7
SMP
GIE/
—
REGISTERS ASSOCIATED WITH SPI OPERATION
SSPOV SSPEN
PORTA Data Direction Register
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
CKE
TMR0IE INT0IE
RCIE
RCIP
RCIF
Bit 5
D/A
Advanced Information
Bit 4
TXIF
TXIE
TXIP
CKP
P
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
(1)
S
TMR0IF
CCP1IF
CCP1IE
CCP1IP
SSPM2
15.3.8
Table 15-1 shows the compatibility between the stan-
dard SPI modes and the states of the CKP and CKE
control bits.
TABLE 15-1:
There is also a SMP bit that controls when the data will
be sampled.
Bit 2
R/W
Standard SPI Mode
Terminology
BUS MODE COMPATIBILITY
0, 0
0, 1
1, 0
1, 1
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
SSPM1
INT0IF
Bit 1
UA
SPI BUS MODES
SSPM0
RBIF
Bit 0
BF
 2000 Microchip Technology Inc.
CKP
Control Bits State
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--11 1111 --11 1111
0000 0000 0000 0000
0
0
1
1
Value on
POR,
BOR
Value on
RESETS
all other
CKE
1
0
1
0