PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 357

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PORTJ
PORTJ Block Diagram ..................................................... 106
PORTK
Postscaler, WDT
Power-down Mode. See SLEEP
Power-on Reset (POR) .............................................. 30, 251
Prescaler, Capture ........................................................... 129
Prescaler, Timer0 ............................................................. 115
Prescaler, Timer1 ............................................................. 118
Prescaler, Timer2 ............................................................. 132
PRO MAT“ II Universal Programmer ............................... 307
Program Counter
Program Memory ............................................................... 41
Program Verification ........................................................ 259
Programmable ................................................................. 251
Programming Time Segments ......................................... 222
Programming, Device Instructions ................................... 261
Propagation Segment ...................................................... 219
PSPCON Register
PWM (CCP Module) ........................................................ 132
Q
Q-Clock ............................................................................ 132
R
RAM. See Data Memory
RCSTA Register
Receive Buffers ................................................................ 213
Receive Buffers Diagram ................................................. 214
Receive Interrupt .............................................................. 225
Receive Message Buffering ............................................. 213
Receiver Error Passive .................................................... 226
Receiver Overrun ............................................................. 226
Receiver Warning ............................................................ 226
Register File ....................................................................... 48
2000 Microchip Technology Inc.
Initialization .............................................................. 106
PORTJ ..................................................................... 106
TRISJ ....................................................................... 106
Initialization .............................................................. 108
PORTK ..................................................................... 108
TRISK ...................................................................... 108
Assignment (PSA Bit) .............................................. 115
Rate Select (PS2:PS0 Bits) ..................................... 115
Switching Between Timer0 and WDT ...................... 115
Oscillator Start-up Timer (OST) ......................... 30, 251
Power-up Timer (PWRT) ................................... 30, 251
Time-out Sequence .................................................... 31
Time-out Sequence on Power-up ........................ 32, 33
Timing Diagram ........................................................ 325
Assignment (PSA Bit) .............................................. 115
Rate Select (PS2:PS0 Bits) ..................................... 115
Switching Between Timer0 and WDT ...................... 115
PCL Register .............................................................. 45
PCLATH Register ...................................................... 45
PSPMODE Bit .................................................... 95, 109
Block Diagram .......................................................... 132
CCPR1H:CCPR1L Registers ................................... 132
Duty Cycle ................................................................ 132
Example Frequencies/Resolutions .......................... 133
Output Diagram ........................................................ 132
Period ....................................................................... 132
Setup for PWM Operation ........................................ 133
TMR2 to PR2 Match ........................................ 121, 132
SPEN Bit .................................................................. 167
Advanced Information
Registers
RESET ....................................................................... 29, 251
Resynchronization ........................................................... 220
RETFIE .................................................................... 291, 292
RETLW ............................................................................ 292
RETURN .......................................................................... 293
Revision History ............................................................... 349
RLCF ............................................................................... 293
RLNCF ............................................................................. 294
RRCF ............................................................................... 294
RRNCF ............................................................................ 295
S
Sample Point ................................................................... 219
SCI. See USART
SCK ................................................................................. 141
SDI ................................................................................... 141
SDO ................................................................................. 141
Serial Clock, SCK ............................................................ 141
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 141
Serial Data Out, SDO ...................................................... 141
Serial Peripheral Interface. See SPI
Shortening a Bit Period .................................................... 221
Simplified Block Diagram of On-Chip Reset Circuit ........... 29
Slave Select Synchronization .......................................... 144
Slave Select, SS .............................................................. 141
SLEEP ............................................................. 251, 257, 296
Software Simulator (MPLAB-SIM) ................................... 306
Special Event Trigger. See Compare
Special Features of the CPU ................................... 247, 251
Special Function Registers ................................................ 48
SPI
SPI Module
SS .................................................................................... 141
SSP ................................................................................. 135
SSP Module
SSPCON1 ....................................................................... 138
SSPCON2 ....................................................................... 140
SSPSTAT ................................................................ 136
T3CON
Timing Diagram ....................................................... 325
Master Mode ............................................................ 143
Serial Clock ............................................................. 141
Serial Data In ........................................................... 141
Serial Data Out ........................................................ 141
Slave Select ............................................................. 141
SPI Clock ................................................................. 143
SPI Mode ................................................................. 141
Slave Mode .............................................................. 144
Slave Select Synchronization .................................. 144
Slave Synch Timing ................................................. 144
Slave Timing with CKE = 0 ...................................... 145
Slave Timing with CKE = 1 ...................................... 145
Block Diagram (SPI Mode) ...................................... 141
I
SPI Mode ................................................................. 141
SPI Mode. See SPI
SSPBUF .................................................................. 143
SSPCON1 ............................................................... 138
SSPCON2 ............................................................... 140
SSPSR .................................................................... 143
SSPSTAT ................................................................ 136
TMR2 Output for Clock Shift ............................ 121, 122
SPI Master Mode ..................................................... 143
SPI Slave Mode ....................................................... 144
2
C Mode. See I
Diagram ........................................................... 123
Section ............................................................ 123
2
C
PIC18CXX8
DS30475A-page 357