PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 211

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

17.3.5
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers, without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself just as if they were
coming from another node. The Loopback mode is a
silent mode, meaning no messages will be transmitted
while in this state, including error flags or acknowledge
signals. The TXCAN pin will revert to port I/O while the
device is in this mode. The filters and masks can be
used to allow only particular messages to be loaded into
the receive registers. The masks can be set to all zeros
to provide a mode that accepts all messages. The Loop-
back mode is activated by setting the mode request bits
in the CANCON register.
17.3.6
The module can be set to ignore all errors and receive
any message. The Error Recognition mode is activated
by setting the RXM<1:0> bits in the RXBnCON regis-
ters to 11. In this mode, the data which is in the mes-
sage assembly buffer until the error time, is copied in
the receive buffer and can be read via the CPU inter-
face. In addition, the data which was on the internal
sampling of the CAN bus at the error time and the state
vector of the protocol state machine and the bit counter
CntCan, are stored in registers and can be read.
17.4
17.4.1
The PIC18CXX8 implements three Transmit Buffers.
Each of these buffers occupies 14 bytes of SRAM and
are mapped into the device memory maps.
For the MCU to have write access to the message buffer,
the TXREQ bit must be clear, indicating that the message
buffer is clear of any pending message to be transmitted.
At a minimum, the TXB
TXB
present in the message, the TXB
be loaded. If the message is to use extended identifiers,
the TXB
EXIDE bit set.
Prior to sending the message, the MCU must initialize
the TXI
interrupt when the message is sent. The MCU must
also initialize the TXP priority bits (see Section 17.4.2).
2000 Microchip Technology Inc.
N
DLC registers must be loaded. If data bytes are
N
N
E bit to enable or disable the generation of an
LOOPBACK MODE
ERROR RECOGNITION MODE
CAN Message Transmission
TRANSMIT BUFFERS
EIDm registers must also be loaded and the
N
SIDH, TXB
N
Dm registers must also
N
Advanced Information
SIDL, and
17.4.2
Transmit priority is a prioritization, within the PIC18CXX8,
of the pending transmittable messages. This is indepen-
dent from, and not related to, any prioritization implicit in
the message arbitration scheme built into the CAN proto-
col. Prior to sending the SOF, the priority of all buffers that
are queued for transmission is compared. The transmit
buffer with the highest priority will be sent first. If two buff-
ers have the same priority setting, the buffer with the
highest buffer number will be sent first. There are four lev-
els of transmit priority. If TXP bits for a particular message
buffer are set to 11, that buffer has the highest possible
priority. If TXP bits for a particular message buffer are 00,
that buffer has the lowest possible priority.
17.4.3
To initiate message transmission, the TXREQ bit must be
set for each buffer to be transmitted.
When TXREQ is set, the TXABT, TXLARB and TXERR
bits will be cleared.
Setting the TXREQ bit does not initiate a message
transmission, it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
When the transmission has completed successfully, the
TXREQ bit will be cleared, the TXBnIF bit will be set, and
an interrupt will be generated if the TXBnIE bit is set.
If the message transmission fails, the TXREQ will remain
set indicating that the message is still pending for trans-
mission and one of the following condition flags will be set.
If the message started to transmit but encountered an
error condition, the TXERR and the IRXIF bits will be set
and an interrupt will be generated. If the message lost
arbitration, the TXLARB bit will be set.
17.4.4
The MCU can request to abort a message by clearing
the TXBnCON.TXREQ bit associated with the corre-
sponding message buffer. Setting CANCON.ABAT bit
will request an abort of all pending messages. If the
message has not yet started transmission, or if the
message started but is interrupted by loss of arbitration
or an error, the abort will be processed. The abort is
indicated when the module sets TXBnCON.ABTF bits.
If the message has started to transmit, it will attempt to
transmit the current message fully. If the current mes-
sage is transmitted fully and is not lost to arbitration or
an error, the ABTF bit will not be set, because the mes-
sage was transmitted successfully. Likewise, if a mes-
sage is being transmitted during an abort request and
the message is lost to arbitration or an error, the mes-
sage will not be re-transmitted and the ABTF bit will be
set, indicating that the message was successfully
aborted.
TRANSMIT PRIORITY
INITIATING TRANSMISSION
ABORTING TRANSMISSION
PIC18CXX8
DS30475A-page 211