PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 159

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

15.4.10 ACKNOWLEDGE SEQUENCE TIMING
An acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2 register). When this bit is set, the SCL pin
is pulled low and the contents of the Acknowledge Data
bit (ACKDT) is presented on the SDA pin. If the user
wishes to generate an acknowledge, then the ACKDT
bit should be cleared. If not, the user should set the
ACKDT bit before starting an acknowledge sequence.
The baud rate generator then counts for one rollover
period (T
high). When the SCL pin is sampled high (clock arbitra-
tion), the baud rate generator counts for T
SCL pin is then pulled low. Following this, the ACKEN
bit is automatically cleared, the baud rate generator is
turned off and the MSSP module then goes into IDLE
mode (Figure 15-17).
15.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-17: ACKNOWLEDGE SEQUENCE WAVEFORM
 2000 Microchip Technology Inc.
BRG
Note: T
) and the SCL pin is de-asserted (pulled
Sequence
SSPIF
Acknowledge sequence starts here,
SDA
SCL
BRG
= one baud rate generator period.
Set SSPIF at the end
of receive
ACKEN = 1, ACKDT = 0
Enable
Write to SSPCON2
bit
8
Advanced Information
D0
BRG
ACKEN
. The
Cleared in
software
T
BRG
ACK
15.4.11 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT register) is set.
A T
is set (Figure 15-18).
15.4.11.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
BRG
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
later, the PEN bit is cleared and the SSPIF bit
ACKEN automatically cleared
PIC18CXX8
Cleared in
software
DS30475A-page 159
BRG