PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 173

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

16.2
In
non-return-to-zero (NRZ) format (one START bit, eight
or nine data bits and one STOP bit). The most common
data format is 8-bits. An on-chip dedicated 8-bit baud
rate generator can be used to derive standard baud
rate frequencies from the oscillator. The USART trans-
mits and receives the LSb first. The USART’s transmit-
ter and receiver are functionally independent, but use
the same data format and baud rate. The baud rate
generator produces a clock, either x16 or x64 of the bit
shift rate, depending on the BRGH bit (TXSTA regis-
ter). Parity is not supported by the hardware, but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
16.2.1
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
FIGURE 16-1: USART TRANSMIT BLOCK DIAGRAM
 2000 Microchip Technology Inc.
this
USART Asynchronous Mode
USART ASYNCHRONOUS TRANSMITTER
mode,
TXIE
Interrupt
the
TXEN
TXIF
Baud Rate Generator
USART
SPBRG
Baud Rate CLK
uses
MSb
(8)
Advanced Information
standard
TX9D
TSR register
TX9
TXREG register
• • •
8
Data Bus
Once the TXREG register transfers the data to the TSR
register (occurs in one T
empty and flag bit TXIF (PIR registers) is set. This inter-
rupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE registers). Flag bit TXIF will be
set, regardless of the state of enable bit TXIE and can-
not be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicated the status of the TXREG register,
another bit TRMT (TXSTA register) shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Note 1: The TSR register is not mapped in data
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts trans-
mission).
LSb
2: Flag bit TXIF is set when enable bit TXEN
0
memory, so it is not available to the user.
is set.
TRMT
Pin Buffer
and Control
PIC18CXX8
SPEN
CY
), the TXREG register is
RC6/TX/CK pin
DS30475A-page 173