S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 94

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12XSPIMV1)
2.3.29
2.3.30
94
Address 0x024A
Address 0x024B
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
RDRS
PERS
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port S reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port S pull device enable—Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
RDRS7
PERS7
Port S Reduced Drive Register (RDRS)
Port S Pull Device Enable Register (PERS)
0
1
7
7
RDRS6
PERS6
Figure 2-28. Port S Pull Device Enable Register (PERS)
0
1
6
6
Figure 2-27. Port S Reduced Drive Register (RDRS)
Table 2-26. RDRS Register Field Descriptions
Table 2-27. PERS Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
RDRS5
PERS5
0
1
5
5
RDRS4
PERS4
0
1
4
4
Description
Description
RDRS3
PERS3
3
0
3
1
RDRS2
PERS2
0
1
2
2
Freescale Semiconductor
RDRS1
PERS1
Access: User read/write
Access: User read/write
0
1
1
1
RDRS0
PERS0
0
1
0
0
1
1