S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 421

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.5.5
This module allows to check for collisions on the LIN bus.
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
Freescale Semiconductor
Output Transmit
•
•
•
•
•
Input Receive
Bit Error
Shift Register
Shift Register
The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
The transmission is aborted and the byte in transmit buffer is discarded.
the transmit data register empty and the transmission complete flag will be set
The bit error interrupt flag, BERRIF, will be set.
No further transmissions will take place until the BERRIF is cleared.
LIN Transmit Collision Detection
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
Receive Shift
Register
Transmit Shift
Register
Compare
Sample
Point
0
1
2
Figure 14-19. Timing Diagram Bit Error Detection
3
Synchronizer Stage
Figure 14-18. Collision Detect Principle
S12XS Family Reference Manual, Rev. 1.11
4
BERRM[1:0] = 0:1
5
Bus Clock
6
7
Compare Sample Points
NOTE
8
9
RXD Pin
TXD Pin
10
11
BERRM[1:0] = 1:1
12
13
Serial Communication Interface (S12SCIV5)
14
LIN Physical Interface
15
0
LIN Bus
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