S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 261

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5.1
The reset sequence is initiated by any of the following events:
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see
Figure
internal reset circuit of the S12XECRG cannot sequence out of current reset condition without a running
SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles
depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released.
The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and then samples the RESET
pin to determine the originating source.
Freescale Semiconductor
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8-21). Since entry into reset is asynchronous it does not require a running SYSCLK. However, the
Low level is detected at the RESET pin (External Reset).
Power on is detected.
Low voltage is detected.
Illegal Address Reset is detected (see S12XMMC Block Guide for details).
COP watchdog times out.
Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
(64 cycles after release)
Description of Reset Operation
Sampled RESET Pin
External circuitry connected to the RESET pin should be able to raise the
signal to a valid logic one within 64 SYSCLK cycles after the low drive is
released by the MCU. If this requirement is not adhered to the reset source
will always be recognized as “External Reset” even if the reset was initially
caused by an other reset source.
1
1
1
0
COP Watchdog Reset
Reset Source
Reset Pending
S12XS Family Reference Manual Rev. 1.11
Clock Monitor
Table 8-17. Reset Vector Selection
Table 8-16. Reset Summary
X
0
1
0
Table 8-17
Reset Pending
NOTE
shows which vector will be fetched.
COP
X
X
0
1
COPCTL (CR[2:0] nonzero)
Illegal Address Reset/ External Reset
Local Enable
S12XE Clocks and Reset Generator (S12XECRGV1)
with rise of RESET pin
Illegal Address Reset/
Clock Monitor Reset
External Reset
Vector Fetch
POR / LVR /
POR / LVR /
COP Reset
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