S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 171

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.1
Register Global Address 0x7FFF01
1
2
3
Freescale Semiconductor
Special Single-Chip Mode
0x7FFF0A
0x7FFF0B
0x7FFF07
0x7FFF08
0x7FFF09
Address
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when
secured if emulation modes available.
UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
Global
Emulation Modes
All Other Modes
(if modes available)
BDMCCRH R
BDMGPR
Reserved
Reserved
Reserved
Register
BDM Status Register (BDMSTS)
Name
Reset
W
R
W
W
W
W
W
R
R
R
R
ENBDM
0
BGAE
1
0
0
7
Bit 7
1
Figure 5-2. BDM Register Summary (continued)
X
0
0
0
0
Figure 5-3. BDM Status Register (BDMSTS)
S12XS Family Reference Manual, Rev. 1.11
= Unimplemented, Reserved
= Always read zero
BDMACT
= Unimplemented, Reserved
= Indeterminate
BGP6
1
0
0
6
6
0
0
0
0
BGP5
0
0
0
0
5
5
0
0
0
0
SDV
BGP4
0
0
0
4
4
0
0
0
0
TRACE
BGP3
0
0
0
3
3
0
0
0
0
0
Background Debug Module (S12XBDMV2)
= Implemented (do not alter)
= Implemented (do not alter)
= Always read zero
CLKSW
CCR10
BGP2
1
0
0
2
2
0
0
0
2
UNSEC
CCR9
BGP1
0
0
0
1
1
0
0
0
3
CCR8
BGP0
Bit 0
0
0
0
0
0
0
0
0
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