S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 129

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1.3
The S12X architecture implements a number of memory mapping schemes including
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1
3.1.4.2
3.1.5
Figure 3-1
Freescale Semiconductor
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a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
a (CPU or BDM) 64KB local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered
as the local map accessed by the 16-bit (CPU or BDM) address.
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
Single chip modes
In normal and special single chip mode the internal memory is used.
S12X Memory Mapping
Modes of Operation
Block Diagram
shows a block diagram of the MMC.
Power Saving Modes
Functional Modes
S12XS Family Reference Manual, Rev. 1.11
Memory Mapping Control (S12XMMCV4)
129