S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 135

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2.4
Read: Anytime. .
Write: Refer to each bit description.
3.3.2.5
Read: Anytime
Freescale Semiconductor
Address: 0x0013 PRR
Address: 0x0015
MGRAMON
PGMIFRON
DFIFRON
Reset
Reset
Field
7
5
4
W
W
R
R
MGRAMON
PIX7
Flash Memory Controller SCRATCH RAM visible in the global memory map
Write: Anytime
This bit is used to made the Flash Memory Controller SCRATCH RAM visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
Data Flash Information Row (IFR) visible in the global memory map
Write: Anytime
This bit is used to made the IFR sector of the Data Flash visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
Program Flash Information Row (IFR) visible in the global memory map
Write: Anytime
This bit is used to map the IFR sector of the Program Flash to address range 0x40_000-0x40_3FFF of the global
memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
MMC Control Register (MMCCTL1)
Program Page Index Register (PPAGE)
0
1
7
7
= Unimplemented or Reserved
PIX6
0
0
1
6
6
Figure 3-11. Program Page Index Register (PPAGE)
Figure 3-10. MMC Control Register (MMCCTL1)
Table 3-6. MMCCTL1 Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
DFIFRON
PIX5
0
1
5
5
PGMIFRON
PIX4
0
1
4
4
Description
PIX3
0
0
1
3
3
PIX2
Memory Mapping Control (S12XMMCV4)
0
0
1
2
2
PIX1
0
0
1
1
1
PIX0
0
0
0
0
0
135