S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 115

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.63
2.3.64
Freescale Semiconductor
Address 0x026D
Address 0x026E
7-6, 1-0
7-6, 1-0
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
Read: Anytime.
PPSJ
Field
Field
PIEJ
Reset
Reset
W
W
R
R
Port J pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
Port J interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
PPSJ7
PIEJ7
Port J Polarity Select Register (PPSJ)
Port J Interrupt Enable Register (PIEJ)
0
0
7
7
PPSJ6
PIEJ6
0
0
6
6
Figure 2-62. Port J Interrupt Enable Register (PIEJ)
Figure 2-61. Port J Polarity Select Register (PPSJ)
Table 2-60. PPSJ Register Field Descriptions
Table 2-61. PIEJ Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
3
0
0
3
0
0
0
0
0
0
Port Integration Module (S12XSPIMV1)
2
2
PPSJ1
Access: User read/write
Access: User read/write
PIEJ1
0
0
1
1
PPSJ0
PIEJ0
0
0
0
0
115
1
1