S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 484

no-image

S9S12XS256J0CAL

Manufacturer Part Number
S9S12XS256J0CAL
Description
MCU 256K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12XS256J0CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XS
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
91
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12XSFAME, EVB9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12XS256J0CAL
Manufacturer:
FREESCALE
Quantity:
3 598
Part Number:
S9S12XS256J0CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S12XS256J0CAL
Manufacturer:
FREESCALE
Quantity:
3 598
Part Number:
S9S12XS256J0CAL
Manufacturer:
FREESCALE
Quantity:
20 000
Timer Module (TIM16B8CV2)
16.4.1
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
484
PACLK/65536
PACLK/256
Bus Clock
PAOVF
INTERRUPT
Prescaler
REQUEST
PR[2:1:0]
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG0A
EDG1A
PAOVF
TCNT(hi):TCNT(lo)
PRESCALER
16-BIT COUNTER
PAOVI
CHANNEL2
CHANNEL 1
CHANNEL7
CHANNEL 0
PACNT(hi):PACNT(lo)
TC0
TC1
TC7
16-BIT COUNTER
EDG7A
EDG7B
EDG0B
EDG1B
INTERRUPT
PAOVI
LOGIC
PACLK/65536
PAOVF
PACLK/256
Figure 16-30. Detailed Timer Block Diagram
S12XS Family Reference Manual, Rev. 1.11
PACLK
CLEAR COUNTER
DETECT
DETECT
TE
DETECT
EDGE
EDGE
EDGE
C0F
C1F
C7F
PAIF
PAI
PACLK
MUX
OM:OL1
OM:OL0
TOV1
OM:OL7
TOV0
TOV7
CLK[1:0]
DIVIDE-BY-64
TOF
TOI
TEN
PEDGE
IOC0
CxF
CxI
C0F
C1F
PAE
IOC1
C7F
IOC7
INTERRUPT
LOGIC
IOC0 PIN
IOC1 PIN
IOC7 PIN
LOGIC
LOGIC
LOGIC
DETECT
EDGE
PAIF
channel 7 output
compare
TCRE
CH. 1 COMPARE
CH. 0 CAPTURE
CH. 1 CAPTURE
CH. 0COMPARE
CH. 7 COMPARE
CH.7 CAPTURE
PA INPUT
Freescale Semiconductor
Bus Clock
IOC0 PIN
IOC1 PIN
IOC7 PIN
TOF

Related parts for S9S12XS256J0CAL