S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 262

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12XE Clocks and Reset Generator (S12XECRGV1)
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles
(External Reset), the internal reset remains asserted longer.
8.5.1.1
The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:
The reset event asynchronously forces the configuration registers to their default settings. In detail the
CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence the
S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the clock
quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the S12XECRG
switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running in parallel to
the reset generator, the S12XECRG may leave Self Clock Mode while still completing the internal reset
sequence.
8.5.1.2
When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period
restarts. If the program fails to do this the S12XECRG will generate a reset.
8.5.1.3
The on-chip voltage regulator detects when V
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the
262
•
•
•
Clock monitor is enabled (CME = 1)
Loss of clock is detected
Self-Clock Mode is disabled (SCME = 0).
Clock Monitor Reset
Computer Operating Properly Watchdog (COP) Reset
Power On Reset, Low Voltage Reset
SYSCLK
RESET
S12XS Family Reference Manual, Rev. 1.11
possibly
SYSCLK
not
running
Figure 8-21. RESET Timing
ICRG drives RESET pin low
) (
DD
128+n cycles
to the MCU has reached a certain level and asserts power
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
) (
)
(
RESET pin
released
64 cycles
)
(
possibly
RESET
driven low
externally
)
(
Freescale Semiconductor