S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 519

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x7F_FF0F located in P-Flash memory (see
indicated by reset condition F in
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Freescale Semiconductor
KEYEN[1:0]
RNV[5:2}
SEC[1:0]
Offset Module Base + 0x0001
Reset
Field
7–6
5–2
1–0
W
R
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
Flash module as shown in
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Flash Security Register (FSEC)
F
7
KEYEN[1:0]
= Unimplemented or Reserved
F
6
1
Preferred KEYEN state to disable backdoor key access.
KEYEN[1:0]
SEC[1:0]
Figure 18-6. Flash Security Register (FSEC)
00
01
10
11
00
01
10
11
Figure
S12XS Family Reference Manual, Rev. 1.11
Table
Table 18-8. FSEC Field Descriptions
Table 18-10. Flash Security States
Table 18-9. Flash KEYEN States
F
5
18-9.
18-6. If a double bit fault is detected while reading the P-Flash
Status of Backdoor Key Access
F
4
Status of Security
RNV[5:2]
Description
UNSECURED
DISABLED
SECURED
DISABLED
DISABLED
SECURED
SECURED
ENABLED
F
3
1
1
256 KByte Flash Module (S12XFTMR256K1V1)
F
2
F
1
Table
Table
SEC[1:0]
18-10. If the
18-3) as
F
0
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