S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 501

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.2.6
The Reserved 06 is reserved for test purposes.
17.3.2.7
The VREGHTTR register allows to trim the VREG temperature sense.
Freescale Semiconductor
0x02F6
0x02F7
Fiption
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
HTTR[3:0]
HTOEN
Reset
Reset
Field
3–0
7
W
W
R
R
HTOEN
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
Reserved 06
High Temperature Trimming Register (VREGHTTR)
High Temperature Trimming Bits — See
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
0
0
0
0
6
6
Bit
Table 17-11. VREGHTTR field descriptions
S12XS Family Reference Manual, Rev. 1.11
Increases V
Increases V
Increases V
Increases V
0
0
0
0
5
5
Table 17-12. Trimming Effect
Figure 17-7. Reserved 06
Figure 17-8. VREGHTTR
HT
HT
HT
HT
twice of HTTR[2]
twice of HTTR[1]
twice of HTTR[0]
(to compensate Temperature Offset)
Table 23-16
0
0
0
0
4
4
Trimming Effect
Description
for trimming effects.
HTTR3
0
0
0
3
3
1
HTTR2
0
0
0
2
2
1
Voltage Regulator (S12VREGL3V3V1)
HTTR1
0
0
0
1
1
1
HTTR0
0
0
0
0
0
1
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