S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 181

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5-7
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.
5.4.6
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
Section 5.3.2.1, “BDM Status Register
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
1.
Freescale Semiconductor
Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
and
Section 5.3.2.1, “BDM Status Register (BDMSTS)”
Hardware
Hardware
Firmware
Firmware
TRACE
Read
Read
Write
Write
GO,
represents the BDM command structure. The command blocks illustrate a series of eight bit
BDM Serial Interface
AT ~16 TC/Bit
Command
Command
Command
Command
Command
8 Bits
DELAY
48-BC
76-BC
Delay
AT ~16 TC/Bit
S12XS Family Reference Manual, Rev. 1.11
Figure 5-7. BDM Command Structure
Address
Address
16 Bits
Data
Command
(BDMSTS)”. This clock will be referred to as the target clock in
Next
Data
for information on how serial clock rate is selected.
DELAY
36-BC
150-BC
Delay
Command
Command
Next
Next
Data
AT ~16 TC/Bit
16 Bits
Background Debug Module (S12XBDMV2)
Data
BC = Bus Clock Cycles
TC = Target Clock Cycles
Section 5.4.6, “BDM Serial Interface”
150-BC
Delay
1
Command
Command
Next
Next
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