S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 118

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12XSPIMV1)
2.3.69
2.3.70
118
DDR1AD0
RDR0AD0
Address 0x0273
Address 0x0274
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
DDR1AD07
RDR0AD07
Port AD0 data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”.
1 Associated pin configured as output
0 Associated pin configured as input
Port AD0 reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port AD0 Data Direction Register 1 (DDR1AD0)
Port AD0 Reduced Drive Register 0 (RDR0AD0)
0
0
7
7
DDR1AD06
RDR0AD06
Figure 2-68. Port AD0 Reduced Drive Register 0 (RDR0AD0)
Figure 2-67. Port AD0 Data Direction Register 1 (DDR1AD0)
0
0
6
6
Table 2-66. DDR1AD0 Register Field Descriptions
Table 2-67. RDR0AD0 Register Field Descriptions
DDR1AD05
RDR0AD05
S12XS Family Reference Manual, Rev. 1.11
0
0
5
5
DDR1AD04
RDR0AD04
0
0
4
4
Description
Description
DDR1AD03
RDR0AD03
3
0
3
0
DDR1AD02
RDR0AD02
0
0
2
2
DDR1AD01
RDR0AD01
Freescale Semiconductor
Access: User read/write
Access: User read/write
0
0
1
1
DDR1AD00
RDR0AD00
0
0
0
0
1
1