S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 420

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communication Interface (S12SCIV5)
Figure 14-17
while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there
will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing
error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later
during the transmission. At the expected stop bit position the byte received so far will be transferred to the
receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate
a parity error will be set. Once the break is detected the BRKDIF flag will be set.
14.4.5.4
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character
length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle
character that begins the first transmission initiated after writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the frame currently being transmitted.
420
Zero Bit Counter
RXD_1
RXD_2
Idle Characters
shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit,
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out through the TXD pin. Setting TE after the
stop bit appears on TXD causes data previously written to the SCI data
register to be lost. Toggle the TE bit for a queued idle character while the
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
Start Bit Position
1
2
Figure 14-17. Break Detection if BRKDFE = 1 (M = 0)
3
S12XS Family Reference Manual, Rev. 1.11
4
Zero Bit Counter
5
6
7
8
NOTE
1
9
Stop Bit Position
2
10
FE = 1
3
BRKDIF = 1
. . .
4
5
6
7
8
9
Freescale Semiconductor
10
BRKDIF = 1
. . .