S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 108

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12XSPIMV1)
2.3.49
2.3.50
108
Address 0x025F
Address 0x0260
Read: Anytime.
Write: Anytime.
Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
Field
Field
PIFP
Reset
Reset
PTH
7-0
7-0
W
W
R
R
Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Port H general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
PIFP7
PTH7
Port P Interrupt Flag Register (PIFP)
Port H Data Register (PTH)
0
0
7
7
PIFP6
PTH6
0
0
6
6
Figure 2-47. Port P Interrupt Flag Register (PIFP)
Table 2-46. PIFP Register Field Descriptions
Table 2-47. PTH Register Field Descriptions
Figure 2-48. Port H Data Register (PTH)
S12XS Family Reference Manual, Rev. 1.11
PIFP5
PTH5
0
0
5
5
PIFP4
PTH4
0
0
4
4
Description
Description
PIFP3
PTH3
3
0
3
0
PIFP2
PTH2
0
0
2
2
Freescale Semiconductor
Access: User read/write
Access: User read/write
PIFP1
PTH1
0
0
1
1
PIFP0
PTH0
0
0
0
0
1
1