S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 174

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Background Debug Module (S12XBDMV2)
5.3.2.2
Register Global Address 0x7FFF06
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
5.3.2.3
Register Global Address 0x7FFF07
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
174
Special Single-Chip Mode
Reset
W
R
All Other Modes
BDM CCR LOW Holding Register (BDMCCRL)
BDM CCR HIGH Holding Register (BDMCCRH)
0
0
7
When BDM is made active, the CPU stores the content of its CCR
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR
BDMCCRL register is read zero.
Reset
L
W
= Unimplemented or Reserved
R
register in this CPU mode. Out of reset in all other modes the
Figure 5-5. BDM CCR HIGH Holding Register (BDMCCRH)
Figure 5-4. BDM CCR LOW Holding Register (BDMCCRL)
CCR7
0
0
6
1
0
7
S12XS Family Reference Manual, Rev. 1.11
CCR6
1
0
6
5
0
0
CCR5
0
0
5
NOTE
0
0
4
CCR4
0
0
4
0
0
3
CCR3
1
0
3
CCR10
2
0
CCR2
0
0
2
L
register
Freescale Semiconductor
CCR9
0
1
CCR1
0
0
1
CCR8
CCR0
0
0
0
0
0