S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 358

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Periodic Interrupt Timer (S12PIT24B4CV1)
12.3.0.8
Read: Anytime
Write: Anytime
358
Module Base + 0x0008, 0x0009
Module Base + 0x000C, 0x000D
Module Base + 0x0010, 0x0011
Module Base + 0x0014, 0x0015
Reset
Reset
Reset
Reset
PLD[15:0]
Field
W
W
W
W
15:0
R
R
R
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
15
15
15
15
0
0
0
0
PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the
PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer
has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits
in the PITFLT register can be used to immediately update the count register with the new value if an immediate
load is desired.
PIT Load Register 0 to 3 (PITLD0–3)
14
14
14
14
0
0
0
0
13
13
13
13
0
0
0
0
12
12
12
12
0
0
0
0
Figure 12-11. PIT Load Register 0 (PITLD0)
Figure 12-12. PIT Load Register 1 (PITLD1)
Figure 12-13. PIT Load Register 2 (PITLD2)
Figure 12-14. PIT Load Register 3 (PITLD3)
Table 12-9. PITLD0–3 Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
11
11
11
11
0
0
0
0
10
10
10
10
0
0
0
0
0
0
0
0
9
9
9
9
Description
0
0
0
0
8
8
8
8
0
0
0
0
7
7
7
7
0
0
0
0
6
6
6
6
0
0
0
0
5
5
5
5
0
0
0
0
4
4
4
4
Freescale Semiconductor
3
0
3
0
3
0
3
0
0
0
0
0
2
2
2
2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0