S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 634

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

64 KByte Flash Module (S12XFTMR64K1V1)
The P-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
following four words addressed by ECCRIX = 010 to 101 contain the 64-bit wide data phrase. The four
data words and the parity byte are the uncorrected data read from the P-Flash block.
The D-Flash word addressed by ECCRIX = 001 contains the lower 16 bits of the global address. The
uncorrected 16-bit data word is addressed by ECCRIX = 010.
20.3.2.15 Flash Option Register (FOPT)
The FOPT register is the Flash option register.
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x7F_FF0E located in P-Flash memory (see
by reset condition F in
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
20.3.2.16 Flash Reserved2 Register (FRSV2)
This Flash register is reserved for factory testing.
All bits in the FRSV2 register read 0 and are not writable.
634
NV[7:0]
Offset Module Base + 0x0010
Offset Module Base + 0x0011
Reset
Reset
Field
7–0
W
W
R
R
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper
use of the NV bits.
F
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure
F
0
0
6
6
Figure 20-23. Flash Reserved2 Register (FRSV2)
20-22. If a double bit fault is detected while reading the P-Flash phrase
Figure 20-22. Flash Option Register (FOPT)
S12XS Family Reference Manual, Rev. 1.11
Table 20-27. FOPT Field Descriptions
F
0
0
5
5
F
0
0
4
4
Description
NV[7:0]
F
0
0
3
3
F
0
0
2
2
Table
Freescale Semiconductor
F
0
0
1
1
20-3) as indicated
F
0
0
0
0