S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 244

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12XE Clocks and Reset Generator (S12XECRGV1)
8.3.2.7
This register controls the IPLL functionality.
244
Module Base + 0x0006
COPWAI
PLLSEL
PLLWAI
RTIWAI
XCLKS
Reset
PSTP
Field
7
6
5
3
1
0
W
R
CME
PLL Select Bit
Write: Anytime.
Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK.
PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as
SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.
0 System clocks are derived from OSCCLK (f
1 System clocks are derived from PLLCLK (f
Pseudo Stop Bit
Write: Anytime
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode.
1 Oscillator continues to run in Stop Mode (Pseudo Stop).
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
Oscillator Configuration Status Bit — This read-only bit shows the oscillator configuration status.
0 Loop controlled Pierce Oscillator is selected.
1 External clock / full swing Pierce Oscillator is selected.
PLL Stops in Wait Mode Bit
Write: Anytime
If PLLWAI is set, the S12XECRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains
set during Wait Mode but the IPLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set
manually if PLL clock is required.
0 IPLL keeps running in Wait Mode.
1 IPLL stops in Wait Mode.
RTI Stops in Wait Mode Bit
Write: Anytime
0 RTI keeps running in Wait Mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.
COP Stops in Wait Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP keeps running in Wait Mode.
1 COP stops and initializes the COP counter whenever the part goes into Wait Mode.
S12XECRG IPLL Control Register (PLLCTL)
1
7
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
PLLON
Figure 8-9. S12XECRG IPLL Control Register (PLLCTL)
1
6
S12XS Family Reference Manual, Rev. 1.11
Table 8-6. CLKSEL Field Descriptions
FM1
0
5
FM0
BUS
0
4
BUS
Description
= f
= f
PLL
OSC
FSTWKP
/ 2).
/ 2).
0
3
PRE
0
2
Freescale Semiconductor
PCE
0
1
SCME
1
0