S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 132

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Mapping Control (S12XMMCV4)
3.3.2.1
Read: Anytime. Write: Only if a transition is allowed (see
The MODE bits of the MODE register are used to establish the MCU operating mode.
132
Address: 0x000B PRR
1. External signal (see
Reset
MODC
Field
Transition done by external pins (MODC)
Transition done by write access to the MODE register
7
W
R
RESET
State
RESET
MODC
MODC
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external
mode pin MODC determines the operating mode during RESET low (active). The state of the pin is latched into
the respective register bit after the RESET signal goes inactive (see
Write restrictions exist to disallow transitions between certain modes.
changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to
these register bits except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
Mode Register (MODE)
7
1
1
Table
= Unimplemented or Reserved
Figure 3-5. Mode Transition Diagram when MCU is Unsecured
Single-Chip
3-2).
Normal
State
(NS)
0
0
6
State
1
S12XS Family Reference Manual, Rev. 1.11
Table 3-3. MODE Field Descriptions
Figure 3-3. Mode Register (MODE)
0
0
5
1
0
0
4
Figure 3-4.
Description
Figure
0
0
3
Single-Chip
3-5).
Special
(SS)
0
Figure
Figure 3-5
0
0
2
3-3).
illustrates all allowed mode
0
Freescale Semiconductor
0
0
1
RESET
0
0
0