S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 125

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port P pins PP[7:3] can be used for either general purpose I/O with pin interrupt capability, or with the
PWM or with the channels of the standard Timer.subsystem.
Port P pins PP[2,0] can be used for either general purpose I/O, or with the PWM or with the TIM or with
the SCI1 subsystem.
Port P pin PP[1] can be used for either general purpose I/O, or with the PWM or with the TIM subsystem.
2.4.3.9
Port H pins PH[7:0] can be used for general purpose I/O with pin interrupt capability.
2.4.3.10
Port J pins PJ[7,6,1,0] can be used for general purpose I/O with pin-interrupt capability.
2.4.3.11
This port is associated with the ATD.
Port AD pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.4
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on a per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
Freescale Semiconductor
2-72).
Pin interrupts
Port H
Port J
Port AD
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
Figure 2-74. Interrupt Glitch Filter on Port P, H and J (PPS=0)
S12XS Family Reference Manual, Rev. 1.11
t
pign
t
pval
(Figure
uncertain
2-75) shorter than a specified time from generating an
Port Integration Module (S12XSPIMV1)
(Figure 2-74
and
125