S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 241

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime
Write: Anytime except if PLLSEL = 1
8.3.2.4
This register provides S12XECRG status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
Module Base + 0x0002
Module Base + 0x0003
Reset
Reset
W
W
R
R
f PLL
RTIF
S12XECRG Flags Register (CRGFLG)
0
0
0
7
=
7
If POSTDIV = $00 then f
------------------------------------- -
(
2xPOSTDIV
f VCO
= Unimplemented or Reserved
= Unimplemented or Reserved
Note 1
PORF
Figure 8-5. S12XECRG Post Divider Register (POSTDIV)
0
0
6
6
Figure 8-6. S12XECRG Flags Register (CRGFLG)
)
S12XS Family Reference Manual Rev. 1.11
Note 2
LVRF
0
0
5
5
PLL
is identical to f
LOCKIF
Note 3
NOTE
0
4
4
VCO
LOCK
0
0
3
3
S12XE Clocks and Reset Generator (S12XECRGV1)
(divide by one).
POSTDIV[4:0]
ILAF
0
0
2
2
SCMIF
0
0
1
1
SCM
0
0
0
0
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