S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 136

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Mapping Control (S12XMMCV4)
Write: Anytime
These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU
or BDM) memory map from address 0x8000 to address 0xBFFF (see
accessing up to 4MB of Flash (in the Global map) within the 64KB Local map. The PPAGE register is
effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
3.3.2.6
136
Address: 0x0016
PIX[7:0]
Reset
Field
7–0
W
R
RP7
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
RAM Page Index Register (RPAGE)
1
7
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
1
Bit21
RP6
1
6
PPAGE Register [7:0]
Figure 3-13. RAM Page Index Register (RPAGE)
S12XS Family Reference Manual, Rev. 1.11
Figure 3-12. PPAGE Address Mapping
Table 3-7. PPAGE Field Descriptions
RP5
1
5
Global Address [22:0]
Bit14
RP4
NOTE
1
4
Description
Bit13
Address: CPU Local Address
RP3
1
3
Address [13:0]
or BDM Local Address
Figure
RP2
1
2
3-12). This supports
Freescale Semiconductor
Bit0
RP1
0
1
RP0
1
0