S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 535

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All bits in the FRSV4 register read 0 and are not writable.
18.4
18.4.1
Flash command operations are used to modify Flash memory contents.
The next sections describe:
18.4.1.1
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz.
values for the FDIV field based on OSCCLK frequency.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
Freescale Semiconductor
Offset Module Base + 0x0013
Reset
•
•
•
W
R
How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
OSCCLK for Flash program and erase command operations
The command write sequence used to set Flash command parameters and launch execution
Valid Flash commands available for execution
Functional Description
Flash Command Operations
Writing the FCLKDIV Register
0
0
7
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 1 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
= Unimplemented or Reserved
0
0
6
Figure 18-25. Flash Reserved4 Register (FRSV4)
S12XS Family Reference Manual, Rev. 1.11
0
0
5
NOTE
0
0
4
0
0
3
256 KByte Flash Module (S12XFTMR256K1V1)
Table 18-7
0
0
2
shows recommended
0
0
1
0
0
0
535