S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 152

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt (S12XINTV2)
4.1.1
The following terms and abbreviations are used in the document.
4.1.2
1.
2.
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The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
The IRQ interrupt can only be handled by the CPU
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Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
One non-maskable system call interrupt vector request (at address vector base + 0x0012).
Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014−
0x0018).
2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).
Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module
I bit maskable interrupts can be nested, depending on their priority levels.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority XGATE and interrupt vector requests, drives the vector to the
XGATE module or to the bus on CPU request, respectively.
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
Glossary
Features
XGATE
Term
XIRQ
MCU
CCR
DMA
IRQ
ISR
INT
IPL
Condition Code Register (in the S12X CPU)
Direct Memory Access
Interrupt
Interrupt Processing Level
Interrupt Service Routine
Micro-Controller Unit
refers to the XGATE co-processor; XGATE is an optional feature
refers to the interrupt request associated with the IRQ pin
refers to the interrupt request associated with the XIRQ pin
S12XS Family Reference Manual, Rev. 1.11
Table 4-2. Terminology
2
Meaning
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1
+ 0x0010).
Freescale Semiconductor