S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 417

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.5
14.4.5.1
The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8
in SCI data register high (SCIDRH) is the ninth bit (bit 8).
14.4.5.2
To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn
are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through
the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data
registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit
shift register.
Freescale Semiconductor
TDRE IRQ
BER IRQ
TC IRQ
Clock
Bus
SBR12:SBR0
Transmitter
Transmitter Character Length
Character Transmission
Baud Divider
PE
PT
M
Generation
÷ 16
Parity
T8
Figure 14-16. Transmitter Block Diagram
S12XS Family Reference Manual, Rev. 1.11
BERRIF
TDRE
TCIE
TCIE
TIE
TC
H
8
7
11-Bit Transmit Register
6
5
SCI Data Registers
4
Internal Bus
Transmitter Control
TE
3
2
Collision Detect
SBK
1
Transmit
0
BERRM[1:0]
L
Serial Communication Interface (S12SCIV5)
TXPOL
CONTROL
LOOP
SCTXD
SCRXD
(From Receiver)
LOOPS
RSRC
To Receiver
SCTXD
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