DS26514G Maxim Integrated, DS26514G Datasheet - Page 96

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

9.12.5 Jitter Attenuator
Each LIU contains a jitter attenuator that can be set to a depth of 32 or 128 bits via the JADS bits in LIU Transmit
and Receive Control Register (LTRCR).
The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used
in delay sensitive applications. The characteristics of the attenuation are shown in
can be placed in either the receive path or the transmit path, or be disabled by appropriately setting the JAPS1 and
JAPS0 bits in the LIU Transmit and Receive Control Register (LTRCR).
For the jitter attenuator to operate properly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x clock must be applied
at MCLK. See the Global Transceiver Clock Control Register 1 (GTCCR1) for MCLK options. ITU-T specification
G.703 requires an accuracy of ±50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an
accuracy of ±32ppm for T1/J1 interfaces. Circuitry adjusts either the recovered clock from the clock/data recovery
block or the clock applied at the TCLKn pin to create a smooth jitter-free clock, which is used to clock data out of
the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKn pin if the jitter attenuator is
placed in the transmit side. If the incoming jitter exceeds either 120UI
depth is 32 bits), then the DS26514 will set the jitter attenuator limit trip (JALTS) bit in the LIU Latched Status
Register (LLSR.3). In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz, and in E1 mode it is 0.6Hz.
The DS26514 jitter attenuator is compliant with the following specifications shown in
Table 9-43. Jitter Attenuator Standards Compliance
Standard
ITU-T I.431, G.703, G.736, G.823
ETS 300 011, TBR 12/13
AT&T TR62411, TR43802
TR-TSY 009, TR-TSY 253, TR-TSY 499
Figure 9-27. Jitter Attenuation
19-5856; Rev 4; 5/11
-20dB
-40dB
-60dB
0dB
1
10
E1
Prohibited
TBR12
Area
T1
100
FREQUENCY (Hz)
1K
P-P
Prohibited Area
(buffer depth is 128-bits) or 28UI
ITU G.7XX
TR 62411 (Dec. 90)
DS26514 4-Port T1/E1/J1 Transceiver
Prohibited Area
10K
Figure
Table
9-27. The jitter attenuator
9-43.
100K
96 of 305
P-P
(buffer