DS26514G Maxim Integrated, DS26514G Datasheet - Page 248

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to
be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be
cleared and set again for a subsequent loads.
Bit 6:Transmit Invert Data Enable (TINV)
Bit 5:Receive Invert Data Enable (RINV).
Bits 4 to 2: Pattern Select Bits 2 to 0 (PS[2:0]). These bits select data pattern used by the transmit and receive
circuits. See
Table 10-26. BERT Pattern Select
Bit 1: Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the
registers BBC1, BBC2, BBC3, BBC4 and BEC1, BEC2, BEC3 and clears the internal count. This bit should be
toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set
again for a subsequent loads.
Bit 0: Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes
to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
19-5856; Rev 4; 5/11
PS2
0
0
0
0
1
1
1
1
0 = Do not invert the outgoing data stream.
1 = Invert the outgoing data stream.
0 = Do not invert the incoming data stream.
1 = Invert the incoming data stream.
PS1
0
0
1
1
0
0
1
1
Table
TC
7
0
PS0
0
1
0
1
0
1
0
1
10-26.
Pseudorandom 2E7–1.
Pseudorandom 2E11–1.
Pseudorandom 2E15–1.
Pseudorandom Pattern QRSS. A 2
Repetitive Pattern.
Alternating Word Pattern.
Modified 55 Octet (Daly) Pattern. The Daly pattern is a repeating 55 octet pattern that is
byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance
for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25
(November 1993).
Pseudorandom 2E-9-1.
BC1
BERT Control Register 1
1105h + (10h x (n - 1)) : where n = 1 to 4
TINV
6
0
RINV
5
0
PS2
4
0
PATTERN DEFINITION
20
- 1 pattern with 14 consecutive zero restriction.
PS1
3
0
DS26514 4-Port T1/E1/J1 Transceiver
PS0
2
0
LC
1
0
RESYNC
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0
0