DS26514G Maxim Integrated, DS26514G Datasheet - Page 74

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

9.10 HDLC Controllers
There are two HDLC Controllers available for each port of the DS26514. HDLC-64 is the default HDLC controller,
which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the
DS26514 beginning with die revision B1. (Note: Older DS26514 die revisions do not have this feature so check
the device errata). The following table describes the features available for each.
Table 9-36. HDLC-64/HDLC-256 Controller Features
9.10.1 HDLC-64 Controller
This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
Mode) or the FDL (T1 Mode). This HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-64 controller, as well as
specific Sa bits (E1 Mode)
The HDLC-64 controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC-64 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
The registers related to the HDLC are displayed in the following table.
Table 9-37
Table 9-37. Registers Related to the HDLC-64
Receive HDLC-64 Control Register
(RHC)
Receive HDLC-64 Bit Suppress
Register (RHBSE)
Receive HDLC-64 FIFO Control
(RHFC)
Receive HDLC-64 Packet Bytes
Available Register (RHPBA)
Receive HDLC-64 FIFO Register (RHF)
Receive Real-Time Status Register 5
(RRTS5)
Receive Latched Status Register 5
(RLS5)
Receive Interrupt Mask 5 (RIM5)
Transmit HDLC-64 Control 1(THC1)
Transmit HDLC-64 Bit Suppress
(THBSE)
Transmit HDLC-64 Control 2 (THC2)
Transmit HDLC-64 FIFO Control
(THFC)
19-5856; Rev 4; 5/11
Transmit HDLC-64 Status (TRTS2)
Transmit HDLC-64 Latched Status
CONTROLLER
HDLC-256
HDLC-64
HDLC
shows the registers related to the HDLC.
REGISTER
FIFO DEPTH
(BYTES)
256
64
MAP TO FDL
Yes
Yes
ADDRESSES
FRAMER 1
0B6h
0B4h
010h
011h
087h
0B5h
094h
0A4h
110h
111h
113h
187h
1B1h
191h
MAP TO
Sa BITS
Yes
Yes
Mapping of the HDLC to DS0 or FDL, Sa Bits
Receive HDLC bit suppression Register
Determines the watermark of the Receive
HDLC FIFO
Tells the user how many bytes are available in
the Receive HDLC FIFO
The actual FIFO data
Indicates the FIFO status
Latched Status
Interrupt Mask for interrupt generation for the
Latched Status
Misc Transmit HDLC Control
Transmit HDLC Bit Suppress for bits not to be
used
HDLC to DS0 channel selection and other
control
Used to control the Transmit HDLC FIFO
Indicates the Real-Time Status of the Transmit
HDLC FIFO
Indicates the FIFO status
DS26514 4-Port T1/E1/J1 Transceiver
SINGLE DS0
MAP TO
Yes
Yes
FUNCTION
Yes, up to 32
MULTIPLE
MAP TO
DS0s
No
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