DS26514G Maxim Integrated, DS26514G Datasheet - Page 80

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

sixteen or more bytes available for storage. If the Receive FIFO is read while the FIFO is empty, the read is
ignored, and an invalid data indication given.
The Transmit FIFO accepts data from the host until full. If the Transmit FIFO is written to while the FIFO is full, the
write is ignored, and a FIFO overflow condition is declared. If the Transmit HDLC Controller attempts to read the
Transmit FIFO while it is empty, a FIFO underflow condition is declared.
The transmit FIFO fill level is available real-time in the Transmit HDLC-256 Status Register 2 (TH256SR2),
indicating the number of bytes that can be written into the transmit FIFO.
9.10.3.2
RH256SRL, RH256SR, TH256SR1, TH256SR2,
controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will
be set to a one. Some of the bits in these registers are latched and some are real-time bits that are not latched.
This section contains register descriptions that list which bits are latched and which are real-time. With the latched
bits, when an event occurs and a bit is set to a one, it will remain set until the user reads and clears that bit. The bit
will be cleared when a ‘1’ is written to the bit and it will not be set again until the event has occurred again. The
real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not
latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to
the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not
affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit
positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear.
The HDLC status registers
output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the
HDLC Interrupt Enable Registers
event occurs. The INTB pin will be allowed to return high (if no other interrupts are present) when the user reads
the event bit that caused the interrupt to occur.
9.10.3.3
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or
a combination of polling and interrupt processes may be used. An example routine for using the DS26514 HDLC
receiver is given in the following figure.
19-5856; Rev 4; 5/11
HDLC-256 Status And Information
Receive HDLC-256 Example
RH256SRL
TH256SRIE
and
TH256SRL
and
RH256SRIE
and
have the ability to initiate a hardware interrupt via the INTB
TH256SRL
. Interrupts will force the INTB signal low when the
provide status information for the HDLC
DS26514 4-Port T1/E1/J1 Transceiver
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