DS26514G Maxim Integrated, DS26514G Datasheet - Page 255

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Description:
Register Address:
Bit #
Name
Default
Bit 7 : Receive All Ones Condition Clear (BRA1C).
Bit 6 : Receive All Zeros Condition Clear (BRA0C).
Bit 5 : Receive Loss Of Synchronization Condition Clear (BRLOSC)
Bit 4 : BERT in Synchronization Condition Clear (BSYNCC).
Bit 3 : Receive All Ones Condition Detect (BRA1D).
Bit 2 : Receive All Zeros Condition Detect (BRA0D).
Bit 1 : Receive Loss Of Synchronization Condition Detect (BRLOSD)
Bit 0 : BERT in Synchronization Condition Detect (BSYNCD).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
All latched bits in this register can create interrupts.
Bit 2: BERT Bit Error Detected Event (BED). A latched bit, which is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 1: BERT Bit Counter Overflow Event (BBCO). A latched bit, which is set when the 32-bit BERT Bit Counter
(BBC) overflows.
Bit 0: BERT Error Counter Overflow Event (BECO). A latched bit, which is set when the 24-bit BERT Error
Counter (BEC) overflows.
19-5856; Rev 4; 5/11
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
BRA1C
7
0
7
0
-
BRA0C
BERT Status Interrupt Mask Register 1
1403h + (10h x (n-1)) : where n = 1 to 4
BLSR2
BERT Latched Status Register 2
1404h + (10h x (n-1)) : where n = 1 to 4
6
0
6
0
-
BRLOSC
5
0
5
0
-
BSYNCC
4
0
4
0
-
BRA1D
3
0
3
0
-
BRA0D
BED
2
0
2
0
BRLOS
DS26514 4-Port T1/E1/J1 Transceiver
BBCO
D
1
0
1
0
BSYNCD
BECO
0
0
0
0
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