DS26514G Maxim Integrated, DS26514G Datasheet - Page 195

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte.
Bit 6: Receive HDLC Data Bit 6 (RHD6)
Bit 5: Receive HDLC Data Bit 5 (RHD5)
Bit 4: Receive HDLC Data Bit 4 (RHD4)
Bit 3: Receive HDLC Data Bit 3 (RHD3)
Bit 2: Receive HDLC Data Bit 2 (RHD2)
Bit 1: Receive HDLC Data Bit 1 (RHD1)
Bit 0: Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Receive Blank Channel Select for Channels 1 to 32 (CH[1:32])
Note that when two or more sequential channels are chosen to be blanked, the receive-slip zone select bit should
be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), then the RSZS bit can be
set to one, which may provide a lower occurrence of slips in certain applications.
19-5856; Rev 4; 5/11
0 = Do not blank this channel (channel data is available on RSERn).
1 = Data on RSERn is forced to all ones for this channel.
(MSB)
CH16
CH24
CH32
CH8
7
RHD7
7
0
CH15
CH23
CH31
CH7
6
RHF
Receive HDLC-64 FIFO Register
0B6h + (200h x (n - 1)) : where n = 1 to 4
RBCS1, RBCS2, RBCS3, RBCS4
Receive Blank Channel Select Registers 1 to 4
0C0h, 0C1h, 0C2h, 0C3h + (200h x (n - 1)) : where n = 1 to 4
RHD6
6
0
CH14
CH22
CH30
CH6
5
RHD5
CH13
CH21
CH29
CH5
5
0
4
CH12
CH20
CH28
CH4
RHD4
3
4
0
CH11
CH19
CH27
CH3
2
RHD3
3
0
CH10
CH18
CH26
CH2
1
DS26514 4-Port T1/E1/J1 Transceiver
RHD2
(LSB)
CH17
CH25
2
0
CH1
CH9
0
RBCS1
RBCS2
RBCS3
RBCS4 (E1
Mode Only)
RHD1
1
0
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RHD0
0
0