DS26514G Maxim Integrated, DS26514G Datasheet - Page 24

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

19-5856; Rev 4; 5/11
D[7]/SPI_CPOL
D[6]/SPI_CPHA
RCHBLK1/
RCHBLK2/
RCHBLK3/
RCHBLK4/
RCHCLK1
RCHCLK2
RCHCLK3
RCHCLK4
RLF/LTC1
BPCLK1
CLKO/
NAME
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
B10
A10
C10
PIN
E4
B5
T5
E8
D3
C8
A8
B8
F8
B9
A9
C9
D9
E9
F9
T9
N9
L6
Output
Output
Output
Output
Output
TYPE
Input/
Input/
Input
MICROPROCESSOR INTERFACE
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK.
RCHBLK[1:4]. RCHBLKn is a user-programmable output that can be forced high
or low during any of the 24 T1 or 32 E1 channels. It is synchronous with RCLKn
when the receive-side elastic store is disabled. It is synchronous with RSYSCLKn
when the receive-side elastic store is enabled. This pin is useful for blocking
clocks to a serial UART or LAPD controller in applications where not all channels
are used such as fractional service, 384kbps service, 768kbps, or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert applications, for external
per-channel loopback, and for per-channel conditioning.
RCHCLK[1:4]. RCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It is synchronous with RCLKn when the receive-
side elastic store is disabled. It is synchronous with RSYSCLKn when the
receive-side elastic store is enabled. It is useful for parallel-to-serial conversion of
channel data.
Backplane Clock 1. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be
RCLK[8:1], a 1.544MHz or 2.048MHz clock frequency derived from MCLK, or an
external reference clock (REFCLKIO). This allows system clocks to be referenced
from external sources, the T1J1E1 recovered clocks, or the MCLK oscillator.
Clock Out. Clock output pin that can be programmed to output numerous
frequencies referenced to MCLK. Frequencies available: 1.544MHz, 2.048MHz,
4.096MHz, 8.192MHz, 12.288MHz, 16.384MHz, 256kHz, and 64kHz.
GTCCR3.CLKOSEL[2:0] selects the frequency.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searching for the
frame and multiframe, or to toggle high if the TCLKn pin has not been toggled for
approximately three clock periods.
RLF/LTC1 is available on the DS26514 when GTCR1.528MD = 1.
Address [12:0]. This bus selects a specific register in the DS26514 during
read/write access. A12 is the MSB and A0 is the LSB.
Data [7]/SPI Interface Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPOL: This signal selects the clock polarity when SPI_SEL = 1. See Section
9.1.2
Data [6]/SPI Interface Clock Phase
D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_CPHA: This signal selects the clock phase when SPI_SEL = 1. See Section
9.1.2
for detailed timing and functionality information. Default setting is low.
for detailed timing and functionality information. Default setting is low.
FUNCTION
DS26514 4-Port T1/E1/J1 Transceiver
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