DS26514G Maxim Integrated, DS26514G Datasheet - Page 221

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 1 and 0: Transmit HDLC-64 FIFO Low Watermark Select (TFLWM[1:0])
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode.
Bit 3: Interleave Bus Operation Enable (IBOEN)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Transmit Channel Monitor Bits (TCM[4:0]). TCM0 is the LSB of a 5-bit channel select that
determines which transmit channel data will appear in the
by a 5-bit BCD code from 0 to 31. TCM[0:4] = all 0s selects channel 1, TCM[0:4] = 11111 selects channel 32.
19-5856; Rev 4; 5/11
TFLWM1
0
0
1
1
0 = Channel Interleave.
1 = Frame Interleave.
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
TFLWM0
—
—
—
7
0
7
0
7
0
0
1
0
1
THFC
Transmit HDLC-64 FIFO Control Register
187h + (200h x (n - 1)) : where n = 1 to 4
TIBOC
Transmit Interleave Bus Operation Control Register
188h + (200h x (n - 1)) : where n = 1 to 4
TDS0SEL
Transmit DS0 Channel Monitor Select Register
189h + (200h x (n - 1)) : where n = 1 to 4
—
—
—
6
0
6
0
6
0
Transmit FIFO Watermark
—
—
5
0
5
0
—
5
0
16 bytes
32 bytes
48 bytes
4 bytes
IBOSEL
TCM4
—
4
0
4
0
4
0
TDS0M
IBOEN
register. Channels 1 through 32 are represented
TCM3
—
3
0
3
0
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TCM2
—
—
2
0
2
0
2
0
TFLWM1
TCM1
—
1
0
1
0
1
0
TFLWM0
221 of 305
TCM0
—
0
0
0
0
0
0