DS26514G Maxim Integrated, DS26514G Datasheet - Page 187

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Receive FIFO Overrun (ROVR)
Bit 4: Receive HDLC Opening Byte Event (RHOBT)
Bit 3: Receive Packet End Event (RPE)
Bit 2: Receive Packet Start Event (RPS)
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS)
Bit 0: Receive FIFO Not Empty Set Event (RNES)
19-5856; Rev 4; 5/11
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
0 = Interrupt masked.
1 = Interrupt enabled.
—
7
0
RIM5
Receive Interrupt Mask 5 (HDLC-64)
0A4h + (200h x (n - 1)) : where n = 1 to 4
—
6
0
ROVR
5
0
RHOBT
4
0
RPE
3
0
DS26514 4-Port T1/E1/J1 Transceiver
RPS
2
0
RHWMS
1
0
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RNES
0
0