DS26514G Maxim Integrated, DS26514G Datasheet - Page 176

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has
cleared (falling edge detect of LORC).
Bit 5: V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has
cleared (falling edge detect of V52LNK).
Bit 4: Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when an RDMA condition has
cleared (falling edge detect of RDMA).
Bit 3: Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLKn pin has not
transitioned for one channel time (rising edge detect of LORC).
Bit 1: V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal.
(G.965). This is the rising edge detect of V52LNK.
Bit 0: Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit-6 of time slot 16 in
frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This
is the rising edge detect of RDMA.
19-5856; Rev 4; 5/11
LORCC
7
0
RLS3 (E1 Mode)
Receive Latched Status Register 3
092h + (200h x (n - 1)) : where n = 1 to 4
—
6
0
V52LNKC
5
0
RDMAC
4
0
RLS3
LORCD
3
0
for T1 Mode.
DS26514 4-Port T1/E1/J1 Transceiver
—
2
0
V52LNKD
1
0
RDMAD
176 of 305
0
0