DS26514G Maxim Integrated, DS26514G Datasheet - Page 79

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

The HDLC-256 controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream. The 256-byte buffers in the
HDLC-256 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
They are also large enough to store an entire frame’s worth of data before requiring host intervention. The
registers related to the HDLC are displayed in the following table.
Receive eXpansion Port Control
Register (RXPC)
Receive HDLC-256 Channel Select
Registers (RHCS1-4)
Receive HDLC-256 Bit Suppress
Register (RHBS)
Receive HDLC-256 Control Register 1
(RH256CR1)
Receive HDLC-256 Control Register 2
(RH256CR2)
Receive HDLC-256 Status Register
(RH256SR)
Receive HDLC-256 FIFO Data
Registers
Transmit eXpansion Port Control
Register (TXPC)
Transmit HDLC-256 Channel Select
Registers (THCS1-4)
Transmit HDLC-256 Bit Suppress
(THBS)
Transmit HDLC-256 Control Register 1
(TH256CR1)
Transmit HDLC-256 Control Register 2
(TH256CR2)
Transmit HDLC-256 FIFO
(TH256FDR1,
Transmit HDLC-256 Status
(TH256SR1, TH256SR2)
Note: The addresses shown above are for Framer 1.
9.10.3.1
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-256 Control Register 2
(RH256CR2) and Transmit HDLC-256 Control Register 2 (TH256CR2). The FIFO Control registers set the
watermarks for the FIFO.
When the receive FIFO fills above the data available level, the RHDA bit (RH256SR.0) will be set. RHDA and
THDA are real-time bits and will remain set as long as the FIFO’s write pointer is above the data available level.
When the transmit FIFO empties below the data storage available level , the THDA bit in the
will be set. THDA is a real-time bit and will remain set as long as the transmit FIFO’s write pointer is below the level
setting. If enabled, this condition can also cause an interrupt via the INTB pin.
If a packet start is received while the receive FIFO is full, the data is discarded and a FIFO overflow condition is
declared (RH256SRL.7). If any other packet data is received while full, the current packet being transferred is
marked with an abort indication, and a FIFO overflow condition is declared. Once a FIFO overflow condition is
declared, the Receive FIFO will discard incoming data until a packet start is received while the Receive FIFO has
19-5856; Rev 4; 5/11
(RH256FDR1, RH256FDR2)
REGISTER
TH256FDR2)
HDLC-256 FIFO Control
151Ch, 151Dh
ADDRESSES
1502h, 1503h
1504h, 1505h
0DCh-0DFh
1DCh-1DFh
FRAMER 1
1510h
1511h
1514h
1500h
1501h
08Ah
08Dh
18Dh
18Ah
Mapping of the HDLC to timeslots or FDL, Sa
Bits
Selection of timeslots to map data to the HDLC
port
Receive HDLC bit suppression Register
Receive Miscellaneous Control
Receive HDLC FIFO Data Level Available
Indicates the FIFO status
The actual FIFO data
Mapping of the HDLC to timeslots or FDL, Sa
Bits
Selection of timeslots to map data from the
HDLC port
Transmit HDLC Bit Suppress for bits not to be
used
Transmit Miscellaneous Control
Indicates the number of bytes that can be
written into the Transmit FIFO
Transmit HDLC FIFO
Indicates the Real-Time Status of the Transmit
HDLC FIFO
DS26514 4-Port T1/E1/J1 Transceiver
FUNCTION
TH256SR1
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register