DS26514G Maxim Integrated, DS26514G Datasheet - Page 217

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 5 and 4 : Transmit Clock Source Select 1 and 0 (TCSS[1:0])
Bit 3: Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe
boundary.
Bit 2: Transmit Frame Mode Select (TFM) (T1 Mode Only)
Bit 1: Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single Bipolar Violation (BPV) to be inserted
into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next
occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent
error to be inserted.
Bit 0 (T1 Mode): Transmit Loop Code Enable (TLOOP). See Section
Bit 0 (E1 Mode): CRC-4 Recalculate (CRC4R)
19-5856; Rev 4; 5/11
TCSS1
0
0
1
1
0 = Normal Operation. Transmit multiframe boundary is determined by 'line-side' counters referenced to
TSYNCn when TSYNCn is an input. Free-running when TSYNCn is an output.
1 = Pass-Forward Operation. Tx multiframe boundary determined by 'system-side' counters referenced to
TSSYNCIOn (input mode3), which is then passed forward to the line side clock domain. This mode can
only be used when the transmit elastic store is enabled with a synchronous backplane (i.e., no frame slips
allowed). This mode must be used to allow Tx hardware signaling insertion while the Tx elastic store is
enabled.
0 = ESF framing mode.
1 = D4 framing mode.
0 = Transmit data normally.
1 = Replace normal transmitted data with repeating code as defined in registers
0 = Transmit CRC-4 generation and insertion operates in normal mode.
1 = Transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method.
TCSS0
0
1
0
1
—
—
7
0
The TCLKn pin is always the source of transmit clock.
Switch to the clock present at RCLKn when the signal at the TCLKn pin fails to transition after
1 channel time.
Reserved.
Use the signal present at RCLKn as the transmit clock. The TCLKn pin is ignored (loop time).
TCR3
Transmit Control Register 3
183h + (200h x (n - 1)) : where n = 1 to 4
—
—
6
0
TCSS1
TCSS1
5
0
TCSS0
TCSS0
4
0
Transmit Clock Source
MFRS
MFRS
3
0
9.9.15
DS26514 4-Port T1/E1/J1 Transceiver
for details.
TFM
—
2
0
T1TCD1
IBPV
IBPV
1
0
and T1TCD2.
217 of 305
TLOOP
CRC4
0
0